IBM will combine copper interconnects with SOI transistors in a range of MPUs next year, and expects performance gains of 20 to 30 percent from the shift to SOI. By applying copper, SOI and low-k interlevel-metal dielectrics to the gigahertz processor design unveiled last February at the International Solid State Circuits Conference, IBM expects to be able to push commercial processor speeds to the gigahertz range by 2000 - a startling three to four years ahead of Intel Corp..

Low voltage SOI applied to the already low voltage PowerPC design further demonstrates IBM/Motorola success in solving the heat and power-dissipation problems which have always plagued Intel's high-performance ICs and offers the mobile market a means of delivering reasonable performance at single-volt supply voltages.

Motorola Inc. indicated last week that it is not far away from applying SOI as well-initially to high-speed logic, starting with a PowerPC. Motorola also is preparing an SOI BiCMOS process aimed at RF/IF circuits used in cellular-phone aF/IF circuits used in cellular-phone applications.

Bijan Davari, director of advanced logic development at IBM, said the company has developed an SOI "recipe" that resolves three major challenges: how to implant and anneal an oxide insulation layer in the bulk silicon at minimal defect rates; how to create partially depleted CMOS devices that can handle the "floating-body" effect common to SOI transistors; and how to prepare relatively accurate models and circuit libraries. The models, in turn, have made it easier to convince circuit designers and product managers to take a risk on SOI-based designs.

Davari said IBM believes the use of SOI wafers adds about 10 percent to the overall process cost of a finished wafer, compared with bulk silicon wafers, while improving performance by 20 to 30 percent. Those gains stem from a sharp reduction in parasitic-junction capacitance.

400 IBM circuit designers, working at four different divisions, have been trained in SOI and are working to apply the technology to a range of circuit designs.  The SOI process already is being installed at IBM's Burlington, Vt., manufacturing complex and will be used fairly quickly to build desktop-PC processors operating in the 1.8- to 2-V range internally.

Ghavam Shahidi, SOI program manager at IBM, said many skeptics even within IBM became believers on Feb. 1, '97, when a PowerPC 604e processor made on SOI-type wafers booted up a compmade on SOI-type wafers booted up a computer. By May '97 a PowerPC 750 processor was booting up.  A four-way server built around a multichip module of four SOI-enhanced PowerPC 750s running IBM's Unix variant, AIX, soon followed.

ViewTouch Note: This is the same processor and operating system used in ViewTouch POS systems.  ViewTouch is the ONLY POS system in the world based on either AIX or on PowerPC processor systems designed to run AIX.

SOI and copper interconnect will soon make big waves on the systems side. The technology gives IBM RS/6000, Motorola PowerPC servers, IBM AS/400 servers and IBM 390 mainframes a formidable performance and reliability lead in the market against systems using Intel's Pentium processors and RISC implementations by other vendors.

Keith Diefendorff, who was the chief PowerPC architect at both Motorola and, later, Apple before joining MicroDesign Resources, said IBM's announcement is "a really big deal" that puts pressure on Intel.

"IBM has gotten a couple of steps ahead," he said. "Copper is a really big deal, and IBM got there well before Intel. They have repeated that with SOI, and the combination of both copper and SOI results in performance gains equal to almost a whole process generation." At 0.18-micron design rules, IBM can apply copper interconnects and SOI-type transistors and get "a pretty big advantage," said Diefendorff.

IBM need not push to the more-expensive lithographic  tools to achieve a performance boost normally gained by shrinking line widths.

Diefendorff said combining SOI with copper will let chip makers reduce the capacitance on both the wires and transistors, and enable higher-clock-rate processors to operate without burning up. But he said that to get to gigahertz speeds, designers must adapt state-of-the-art processor designs to SOI, starting from the ground up.

Diefendorff and others noted that Intel researchers-in  their public pronouncements at chip conferences-have  been conservative about using SOI.

The long route to commercial use of SOI still contains some cost hurdles.  IBM started SOI research in earnest in the mid-1980s, when researchers concluded it would be hard to  scale bulk silicon-based circuits down to low voltages.  The effort picked up momentum in 1990, when Shahidi and others showed that a partially depleted CMOS (rather than fully depleted) could overcome the short-channel effect common to fully depleted devices  in SOI wafers.

IBM implants a thin, 3,500-angstrom layer of oxide beneath a silicon layer of1,800 angstrom on a non-epitaxial wafer. IBM developed a proprietary furnace annealing process step.  The result is wafers with defect rates comparable to bulk silicon at "reasonable" throughput in the wafer-creation stage.  Thele to bulk silicon at "reasonable" throughput in the wafer-creation stage.  The slow process of implanting the oxygen, now done internally at IBM at a rate of about 20 wafers per day per implanter, results in an SOI wafer cost of about $400 to $500, compared with about $60 for a bulk silicon 8-inch wafer at that early stage. In a finished wafer, which might cost several  thousand dollars, the cost differential between the SOI and CMOS process shrinks to 10 percent.

Shahidi said the cost difference between early-stage SOI  and CMOS wafers can be reduced two to four times with higher-throughput equipment.

IBM and Motorola have worked with Ibis Technologies Corp. (Danvers, MA) which has  developed implantation machines that allow oxygen to  be diffused into the silicon with no appreciable increase in defects in the crystal lattice. Ibis sold two implanters to IBM and a third to wafer manufacturer Mitsubishi Materials Corp. It has  also licensed its technology to Mitsubishi Materials.

Al Alioto, Ibis Sales VP, said that at lower voltages the thickness of the oxide layer can be reduced, shortening the time needed to implant a single wafer from five hours for a 3,500-angstrom layer needed at 1.8-V operation to 1,000 angstrom or less, with a proportional reduction in the implant time. That would serve to improve throughput and reduce costs for volume SOI production.  "At 1.5 V you don't need such a thick layer.  The SOI approach really starts to make sense for high-performance CMOS." he said.

IBM has company in SOI manufacturing.  Jim Prendergast, director of Motorola's wireless IC research and development laboratory, said Motorola is "well beyond the R&D stage with thin-film SOI. We are looking at products where thin-film SOI has clear advantages."  Motorola has fabricated a test vehicle, believed to be a PowerPC processor, at its Advanced Technology Line in Austin, Texas, which Prendergast said "can be developed for production in 1999."

Motorola also has undertaken a BiCMOS process development in SOI for RF/IF applications. Getting sufficient gain in SOI has been difficult, Prendergast said, and dealing with electrostatic discharge also has been a challenge. He said applying SOI at the 0.15-micron technology generation is on Motorola's technology road map. "Motorola is in quite a strong position in thin-film SOI."

In Japan, Mitsubishi Electric has begun offering samples of a 500,000-gate array in SOI technology. Honeywell's Plymouth, Minn., operation uses SOI technology for space applications and other radiation-hardened circuits, and is extending that work to SOI-based sensors. Peregrine Semiconductor (San Diego) has pioneered silicon-on-sapphire technology for satellite and cellular-phone applications.

Fred Zieber, principal analyst at Pathfinder Research, said SOI presents manufacturers with a number of challenges, and it may take two years or more for even Intel to catch up to IBM and Motorola. Zieber said,"SOI takes a lot of elbow grease, and it takes companies like IBM and Motorola to pull something like this off." 
 
 
 
 
 
 

SOI will increase the power efficiency of DSPs, ASICs, and other chips used in cellular handsets and portable electronic devices.   In combination with the copper-interconnect wiring scheme the company unveiled last September, SOI also reduces power consumption to one-third of normal operating levels, tripling battery life.

By rolling these two techniques into a single production process, IBM and Motorola are padding the lead of PowerPC semiconductor technology at least two years ahead of the industry, analysts said.  "It's an important step," said Fred Zieber, president of Pathfinder Research, San years ahead of the industry, analysts said.  "It's an important step," said Fred Zieber, president of Pathfinder Research, San Jose. "I think we'll hear of a lot of people working on it down the road, but IBM and Motorola are far ahead of the competition."

Such advances in chip processing technology follow the demand for devices that pack more performance and  functions into a smaller space. Moving chips to higher operating speeds requires more power, but "IBM is bringing two distinct technologies together to further improve the performance  characteristics and actually lower the net power consumption of  ever-faster chips," said Will Strauss, president of Forward Concepts Co., Tempe, Ariz.

Nearly every major IC house has experimented with  SOI. For 30 years, researchers have been trying to bring the technology into commercial use but the expense and technical problems of implementing a fundamentally new process have limited its use to niche IC production.  "There have been a number of false starts and offshoot technologies that have failed but the basic principles were sound," said Bijan Davari, IBM fellow and director of advanced logic technology development for IBM Microelectronics. "We have finally found the recipe for applying SOI in a real manufacturing environment for real products."

SOI refers to a thin layer of silicon placed on top of an insulation layer, such as silicon oxide or glass, which reduces the transistor capacitance that consumes power and slows the chip dthat consumes power and slows the chip down.  Copper interconnects have a similar effect on speed by reducing capacitance through the chip's wire circuitry.

Although wafers made with the SOI technique are commercially available, IBM said it will make its own to ensure the quality of the base wafer.  SOI adds an implant step, adding about 10% to the cost of the wafer. Customers are willing to pay extra for the value the technology delivers, according to analysts.

"There's a whole lot of elbow grease involved in bringing a new process technology to the forefront," Zieber said.  "But it's exciting and it's interesting to the strategies of IBM and Motorola to be a process leader at a time when we don't have a lot of companies putting money into fundamental process improvements."

The significance of the market and performance advantages of the two technologies obviously played a big role in the recent patent portfolio agreements which Europe's ST Microelectronics (formerly SGS-Thomsen) and Japan's Sanyo recently concluded with IBM.  The recent Embedded PowerPC technology-sharing agreement with Motorola makes it very clear that IBM and Motorola both intend not only to maintain their dominance in the embedded device market, a market far larger than the desktop seminconductor market, but to make it very difficult for Intel to even hang on to the minimal presence it does have in the embedded market.

Wafer-level burn-in technology promises to lower chip-manufacturing costs as much as 15 percent, and shorten production cycles by 25 percent, said managers involved with the project in Motorola's Semiconductor Products sector. 

For the past 18 months, Motorola has collaborated with capital-equipment maker Tokyo Electron, and interconnect supplier W.L. Gore and Associates to create production systems that will force early failures in marginal and defective devices before silicon wafers are sent to assembly plants for final packaging and test. The first production systems will be used in a wafer-level burn-in pilot line slated to begin operations in Austin, Texas during the first quarter of 1999. 

"We will get an opportunity to sort out the good products while they are still on wafers, before we have spent money packaging the parts," said Les Hazlett, manager of strategic final manufacturing operations for Motorola's semiconductor unit. "As the die becomes more complex, the number of inputs/outputs increases and the package becomes more expensive." 

Wafer-level burn-in is a key step toward the ultimate goal of performing full device testing before silicon substrates are cut into individual chips and packaged.  Motorola intends to create a wafer-level test system that will work in conjunction with the burn-in technology to dramatically reduce or even eliminate the need for automatic test equipment (ATE) of packaged parts. 

"Wafer-level burn-in is an enabling technology to allow for true wafer-level tests." Hazlett said. "We are still going to be a major user of testers [once wafer-level test is ready], but we hope to buy fewer of them." 

 Studies by Austin-based Microelectronics and Computer Technology Corp. (MCC), an industry consortium, show that wafer-level burn-in and tests could result in cost savings of more than 50 percent when chip volumes exceed one million units a year. MCC has also been involved in organizing a collaborative effort to create commercial wafer-level burn-in and test systems with memory makers and system suppliers. 

Motorola's initial wafer-level burn-in systems will be used in its bump-assembly-test BAT 1 production line in Austin to cut costs and speed completion of fast static RAMs, Power PC reduced instruction-set computer processors, and microcontrollers. To do that, Motorola teamed with Japan's TEL and W.L. Gore of Elkton, Md., to create production-worthy systems. 

In the project, W.L. Gore provided the interconnect substrates and boards for wafer contacts. TEL provided equipment expertise. Motorola has formed a joint venture with TEL to make further improvements to the burn-in technology so it can be used in volume production along with wafer probers that check out each die for device failures. Over time, the capabilities of wafer probers will be enhanced to eventually perform full tests of devices. 

Wafer-level burn-in boosts good die products because it eliminates the need for special chip carriers to heat and test bare ICs.  "While our motivation is to achieve improvements over burn-in of packaged parts, wafer-level burn-in allows us to create a manufacturing process that's much simpler," Hazlett said.

An advanced new technology which allows
burn-in testing of integrated circuits at the wafer level was announced by Motorola Semiconductor Products Sector, Tokyo Electron Limited (TEL), and W.L. Gore and Associates Inc. (GORE). 

Through simplification and consolidation of product testing operations, manufacturing cost savings are expected to be as high as 15 percent and improvements in manufacturing cycle time will range up to 25 percent.  The companies predict the new technique will provide significant reductions in development cycle time and capital investments. 

The agreement is the culmination of an 18-month joint effort by Motorola, TEL and GORE to demonstratuctions in development cycle time and capital investments. 

The agreement is the culmination of an 18-month joint effort by Motorola, TEL and GORE to demonstrate and test a new process to "burn in" semiconductor devices while they are still in wafer form. With this announcement, Motorola and TEL are entering into a more formal joint development effort to prove the technology and deploy it in production of leading-edge semiconductor products. 

Motorola expects to begin using this new manufacturing technology in 1999.  "This process is a new paradigm for the industry that will dramatically change the layout and process flow of wafer manufacturing and assembly facilities," said Bill Walker, senior vice president and director of Sector Manufacturing for Motorola. "It also represents a major step toward improvement of our overall manufacturing cycle time." 

The new  burn-in testing approach uses TEL wafer-prober technology in a controlled environment and allows each chip on a silicon wafer to be electrically stressed across a range of temperatures from 125 C to 150 C. The technique initially was designed to test chips which use the "bump" style interconnect technology, associated with high-performance, leading-edge products. Ultimately, all types of semiconductors will be tested. 

Using this new technology, a silicon wafer of completed circuits is placed on a thermal chuck with an extremely flat surface. An electrical contact head, with thousands of contacts, is aligned to the wafer and contact is made through a sheet of contact material. 

Critical to the process is the unique full-wafer contact material, called GoreMate(TM) wafer contactor, placed between the contact head and the test wafer. GORE also developed a thermally matched (Inferno(TM)) interconnect board, designed to have the same coefficient of expansion as silicon.  Ensuring contact integrity at burn-in temperatures is considered one of the greatest technical challenges for the wafer-level burn-in process. 

"This development, from our point of view, is a key technology for revolutionary improvement in the future back-end semiconductor production process. The realization of this development -- technology and equipment -- will prompt rapid improvement in the efficiency of the back-end wafer test process and acceleration in the realization of the coming distribution of "known good die" (high-quality bare chips) and wafer-level chips," said Terry Higashi, chief executive officer, president of TEL. 

Motorola is taking this major step forward as part of its ongoing improvement of semiconductor manufacturing methods. Making burn in a wafer-level operation significantly reduces the handling and testing of packaged units. Burn in, as a wafer-processing operation, also reduces cycle time for reliability testing -- helping to reduce overall cycle time for new product introductions.